The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

this course is given good idea of Hardware Description Language and i understood the concepts well.

Course content is moderate. But also have complexity level higher for a beginner.

A very engaging course to do for beginners having fundamentals strong.

Explanations are not that good for some circuits like memory

There should have been more examples of problems.

a big thank you to all the professiors

It should be more elaborative

BEST FOR THE BASIC

good

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

the course is arranged well but the teaching methodology is not good the teachers are just reading the ppts secondly assignments submission way is troublesome

Videos could be better, felt it was too fast and didn't cover the concepts well enough

Verilog part is explained very well but VHDL part completely unsatisfied.