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Voltar para Hardware Description Languages for FPGA Design

Comentários e feedback de alunos de Hardware Description Languages for FPGA Design da instituição Universidade do Colorado em Boulder

275 classificações
77 avaliações

Sobre o curso

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Melhores avaliações


Jun 05, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .


Jul 31, 2020

The course helped in showing the different styles of the Verilog and VHDL coding.\n\nUnderstood the advantages of Verilog and VHDL in real life applications

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51 — 75 de 80 Avaliações para o Hardware Description Languages for FPGA Design


Jun 29, 2020

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

por pedram k

Apr 21, 2020

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.


May 15, 2020

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

por Borys I

Aug 29, 2020

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.


May 17, 2020

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

por Timothy

May 01, 2020

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.


May 16, 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

por Rohit l

May 02, 2020

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

por harsh

May 15, 2020

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

por Rishi J

Sep 04, 2020

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

por Aishwarya S

May 07, 2020

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

por Raghul R

Jun 25, 2020

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.


May 14, 2020

this course is given good idea of Hardware Description Language and i understood the concepts well.

por Muhammad Z Y

Apr 08, 2020

Course content is moderate. But also have complexity level higher for a beginner.

por Apoorva S

May 25, 2020

A very engaging course to do for beginners having fundamentals strong.

por Yuvraj S R

May 18, 2020

Explanations are not that good for some circuits like memory

por Sourav N

Sep 18, 2020

There should have been more examples of problems.


Apr 30, 2020

a big thank you to all the professiors

por Prakash K R

Jun 24, 2020

It should be more elaborative


Jun 07, 2020


por J S

Aug 05, 2020


por Islam E

May 31, 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

por Saran z

Apr 25, 2020

the course is arranged well but the teaching methodology is not good the teachers are just reading the ppts secondly assignments submission way is troublesome

por V S V

Sep 29, 2020

Videos could be better, felt it was too fast and didn't cover the concepts well enough

por Harsh A

Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.