This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
oferecido por
Hardware Description Languages for FPGA Design
Universidade do Colorado em Boulder
Informações sobre o curso
63,187 visualizações recentes
Habilidades que você terá
Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
100% on-line
Comece imediatamente e aprenda em seu próprio cronograma.
Prazos flexíveis
Redefinir os prazos de acordo com sua programação.
Nível intermediário
Aprox. 30 horas para completar
Sugerido: 4 weeks of study, 8-12 hours/week
Inglês
Legendas: Inglês
oferecido por
Universidade do Colorado em Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Comece a trabalhar rumo ao seu mestrado
Este curso é parte da graduação 100% on-line Master of Science in Electrical Engineering da Universidade do Colorado em Boulder.
Caso seja aceito para o programa completo, seus cursos contarão para sua graduação.
Programa - O que você aprenderá com este curso
8 horas para concluir
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 horas para concluir
10 vídeos (Total 48 mín.), 2 leituras, 6 testes
10 videos
Why Learn VHDL?1min
FPGA Design Flow3min
Intro to VHDL: Finite State Machine3min
How to speak VHDL, first phrases6min
VHDL Assignments, Operators, Types3min
VHDL Rules and Syntax, Interface Ports3min
VHDL in ModelSim: Download and Install3min
VHDL in ModelSim: Adding to your Toolkit6min
Submitting VHDL Programming Assignments11min
2 leituras
Misson 2-001: Week 1 Readings2h
Files for Week 1 Programming Assignments10min
2 exercícios práticos
VHDL Find the Code Errors30min
Module 1 Quiz30min
12 horas para concluir
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 horas para concluir
10 vídeos (Total 52 mín.), 2 leituras, 6 testes
10 videos
Combinatorial Circuits4min
Synchronous Logic: Latches and Flip Flops4min
Synchronous Logic: Counters and Registers6min
Buses and Tristate Buffers3min
Modular Designs: Components, Generate and Loops in VHDL3min
Test Benches in VHDL: Combinatorial8min
Test Benches in VHDL: Synchronous5min
Memory in VHDL7min
Finite State Machines in VHDL8min
2 leituras
Week 2 Readings2h
Files for Week 2 Programming Assignments10min
1 exercício prático
Module 2 Quiz30min
7 horas para concluir
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 horas para concluir
9 vídeos (Total 92 mín.), 2 leituras, 6 testes
9 videos
Your First Verilog phrase11min
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12min
Verilog Statements and Operators16min
Verilog Modules, Port Modes and Data Types10min
Verilog Structure10min
Testing with ModelSim5min
Verilog Evaluation11min
Submitting Verilog Programming Assignments10min
2 leituras
Week 3 Readings1h 10min
Files for Week 3 Programming Assignments10min
2 exercícios práticos
Verilog Find the Errors20min
Module 3 Quiz30min
10 horas para concluir
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 horas para concluir
10 vídeos (Total 48 mín.), 2 leituras, 6 testes
10 videos
Combinatorial Circuits5min
Synchronous Logic: Latches and Flip Flops3min
Synchronous Logic: Counters and Registers5min
Buses and Tristate Buffers3min
Modular Design in Verilog3min
Testbenches in Verilog7min
Testbenches in Verilog II2min
Memory with Verilog4min
Verilog Finite State Machines7min
2 leituras
Week 4 Readings15min
Files for Week 4 Programming Assignments10min
1 exercício prático
Module 4 Quiz30min
Avaliações
Principais avaliações do HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
por VVJan 15, 2020
Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.
por WAMar 21, 2020
This course really great and have a lot of fun to learn FPGA Designs.
por PDMar 17, 2020
Great course with in-depth explanations of HDL with Verilog and VHDL
Perguntas Frequentes – FAQ
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