University of Colorado Boulder
Hardware Description Languages for FPGA Design
University of Colorado Boulder

Hardware Description Languages for FPGA Design

This course is part of FPGA Design for Embedded Systems Specialization

Taught in English

Some content may not be translated

Timothy Scherr
Benjamin Spriggs

Instructors: Timothy Scherr

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Course

Gain insight into a topic and learn the fundamentals

4.4

(548 reviews)

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80%

Intermediate level
Some related experience required
36 hours (approximately)
Flexible schedule
Learn at your own pace
Progress towards a degree

What you'll learn

  • Explain the role of HDLs in design entry and verification for FPGAs and ASICs

  • Utilize HDL software tools for FPGA development

Details to know

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Assessments

6 quizzes

Course

Gain insight into a topic and learn the fundamentals

4.4

(548 reviews)

|

80%

Intermediate level
Some related experience required
36 hours (approximately)
Flexible schedule
Learn at your own pace
Progress towards a degree

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This course is part of the FPGA Design for Embedded Systems Specialization
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There are 4 modules in this course

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

What's included

10 videos3 readings2 quizzes4 programming assignments1 discussion prompt

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

What's included

10 videos2 readings1 quiz5 programming assignments

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

What's included

9 videos2 readings2 quizzes4 programming assignments

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

What's included

10 videos2 readings1 quiz5 programming assignments

Instructors

Instructor ratings
4.3 (213 ratings)
Timothy Scherr
University of Colorado Boulder
5 Courses94,997 learners

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Recommended if you're interested in Electrical Engineering

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