This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Este curso faz parte do Programa de cursos integrados FPGA Design for Embedded Systems
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Programa de cursos integrados FPGA Design for Embedded SystemsUniversidade do Colorado em BoulderInformações sobre o curso
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Prazos flexíveis
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Certificados compartilháveis
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100% on-line
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Nível intermediário
Aprox. 36 horas para completar
Inglês
Legendas: Árabe, Francês, Portuguese (European), Italiano, Vietnamita, Alemão, Russo, Inglês, Espanhol
Habilidades que você terá
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
Prazos flexíveis
Redefinir os prazos de acordo com sua programação.
Certificados compartilháveis
Tenha o certificado após a conclusão
100% on-line
Comece imediatamente e aprenda em seu próprio cronograma.
Nível intermediário
Aprox. 36 horas para completar
Inglês
Legendas: Árabe, Francês, Portuguese (European), Italiano, Vietnamita, Alemão, Russo, Inglês, Espanhol
oferecido por
Universidade do Colorado em Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
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Este curso é parte de um programa de graduação on-line oferecido por Universidade do Colorado em Boulder. Quando você se inscreve através de uma universidade em um curso sem diploma, mas que conta com créditos e o completa on-line, ele conta como horas complementares na graduação da CU-Boulder. Você só precisa se inscrever pela universidade.
Programa - O que você aprenderá com este curso
8 horas para concluir
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 horas para concluir
10 vídeos (Total 48 mín.), 3 leituras, 6 testes
12 horas para concluir
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 horas para concluir
10 vídeos (Total 52 mín.), 2 leituras, 6 testes
7 horas para concluir
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 horas para concluir
9 vídeos (Total 92 mín.), 2 leituras, 6 testes
10 horas para concluir
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 horas para concluir
10 vídeos (Total 48 mín.), 2 leituras, 6 testes
Avaliações
- 5 stars58,21%
- 4 stars28,48%
- 3 stars7,06%
- 2 stars3,11%
- 1 star3,11%
Principais avaliações do HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
por MS15 de mai de 2020
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
por JV23 de fev de 2021
Professors were top-notch and clearly explained the pros and cons of each of the languages. I hope I could meet them in person.
por AS6 de mai de 2020
FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.
por JS6 de jun de 2021
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
Sobre Programa de cursos integrados FPGA Design for Embedded Systems
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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