Chevron Left
Voltar para Hardware Description Languages for FPGA Design

Comentários e feedback de alunos de Hardware Description Languages for FPGA Design da instituição Universidade do Colorado em Boulder

275 classificações
77 avaliações

Sobre o curso

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Melhores avaliações


Jun 05, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .


Jul 31, 2020

The course helped in showing the different styles of the Verilog and VHDL coding.\n\nUnderstood the advantages of Verilog and VHDL in real life applications

Filtrar por:

26 — 50 de 80 Avaliações para o Hardware Description Languages for FPGA Design

por Jakub L

Jul 08, 2020

Very nice entry level course, teaches the basic concepcts very clearly, overall great.

por silpa k v

May 06, 2020

Good description and Way of explaining.

Forums helping out more.


por Ranjan Y

Apr 18, 2020

The course is best for beginners and very useful to practice the basics.

por Waseem A

Mar 22, 2020

This course really great and have a lot of fun to learn FPGA Designs.

por Chathura J G

Jul 07, 2020

Best Course I ever had. Lectures are extremely talented in teaching.

por Phanindra D

Mar 18, 2020

Great course with in-depth explanations of HDL with Verilog and VHDL

por Orzumamadov G M

Jul 10, 2020

Thanks to the authors for such an interesting and useful course.

por kasani J g

May 05, 2020

it is really fun to learn this course you will really enjoy it,


Sep 29, 2020

Great course to explore the comparison of VHDL and Verilog.

por mandeep s r

Aug 01, 2020

This is one of the best courses available on coursera.

por Mahendra V

Jun 06, 2020

Good Learning with structured assignments.

por himanshu g

Mar 29, 2020

A Nice Course which required more hardwork

por Soorya K

May 08, 2020

Assignment programs are very challenging.


Jul 07, 2020

extremely short crisp and knowledgeable

por Apurba D

Aug 09, 2020

Liked the programming assignments...

por Patrick M

Aug 02, 2020

good mix between theory and practice

por Ehtesham A K

May 19, 2020

Excellent Course for FPGA learners.

por P S

Aug 06, 2020

Very well explained the concepts.

por Kondapally M R

Jun 24, 2020

very informative and practical


Aug 31, 2020

this course is very nice.

por Vinayakumar R B

May 26, 2020

Very good for beginners

por Rinson V

Aug 17, 2020

Very good course

por Mucha. S r

Aug 27, 2020

Awesome course

por Lalit B

Mar 04, 2020

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

por Samer A A

Jul 07, 2020

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.