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Voltar para VLSI CAD Part II: Layout

VLSI CAD Part II: Layout, University of Illinois at Urbana-Champaign

4.8
30 classificações
5 avaliações

Informações sobre o curso

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....
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5 avaliações

por Akash Levy

Oct 21, 2018

Great basic overview of the core design principles for EDA

por Mohammad Hizzani

Sep 01, 2018

It was a great experience, really great lecturer without exaggerating, but the programming assignment 3 (which is optional) was totally a nightmare, I wrote about 1000 line of code to do both the essential and the extra parts, but not yet.

I hope there was another course for design using HDL like Verilog or System Verilog.

por Pankaj Mudgil

Aug 16, 2018

Very good to learn algorithms!

por Kanishka Sharma

Jun 30, 2018

Excellent course, very helpful!

por BHARATH KESHAVAMURTHY

Oct 31, 2017

Amazing!!!