Informações sobre o curso
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You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....
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cursos 100% online

Comece imediatamente e aprenda em seu próprio cronograma.
Calendar

Prazos flexíveis

Redefinir os prazos de acordo com sua programação.
Intermediate Level

Nível intermediário

Clock

Sugerido: 6 hours/week

Aprox. 21 horas restantes
Comment Dots

English

Legendas: English
Globe

cursos 100% online

Comece imediatamente e aprenda em seu próprio cronograma.
Calendar

Prazos flexíveis

Redefinir os prazos de acordo com sua programação.
Intermediate Level

Nível intermediário

Clock

Sugerido: 6 hours/week

Aprox. 21 horas restantes
Comment Dots

English

Legendas: English

Programa - O que você aprenderá com este curso

1

Seção
Clock
1 hora para concluir

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course....
Reading
2 vídeos (Total de 23 min), 2 leituras, 1 teste
Video2 videos
Two Tools Tutorial4min
Reading2 leituras
Syllabus10min
Tools For This Course10min
Quiz1 exercício prático
Demographics Survey5min
Clock
3 horas para concluir

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks....
Reading
9 vídeos (Total de 163 min), 2 leituras
Video9 videos
Basics17min
Wirelength Estimation15min
Simple Iterative Improvement Placement12min
Iterative Improvement with Hill Climbing15min
Simulated Annealing Placement27min
Analytical Placement: Quadratic Wirelength Model14min
Analytical Placement: Quadratic Placement26min
Analytical Placement: Recursive Partitioning18min
Analytical Placement: Recursive Partitioning Example16min
Reading2 leituras
Week 1 Overview10min
Week 1 Assignments10min

2

Seção
Clock
6 horas para concluir

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD....
Reading
6 vídeos (Total de 102 min), 2 leituras, 2 testes
Video6 videos
Technology Mapping as Tree Covering29min
Technology Mapping—Tree-ifying the Netlist13min
Technology Mapping—Recursive Matching9min
Technology Mapping—Minimum Cost Covering16min
Technology Mapping—Detailed Covering Example14min
Reading2 leituras
Week 2 Overview10min
Week 2 Assignments10min
Quiz1 exercício prático
Problem Set #1min

3

Seção
Clock
4 horas para concluir

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment....
Reading
9 vídeos (Total de 145 min), 2 leituras, 1 teste
Video9 videos
Maze Routing: 2-Point Nets in 1 Layer16min
Maze Routing: Multi-Point Nets12min
Maze Routing: Multi-Layer Routing12min
Maze Routing: Non-Uniform Grid Costs14min
Implementation Mechanics: How Expansion Works23min
Implementation Mechanics: Data Structures & Constraints18min
Implementation Mechanics: Depth First Search14min
From Detailed Routing to Global Routing15min
Reading2 leituras
Week 3 Overview10min
Week 3 Assignments10min
Quiz1 exercício prático
Problem Set #2min

4

Seção
Clock
7 horas para concluir

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design....
Reading
8 vídeos (Total de 148 min), 2 leituras, 2 testes
Video8 videos
Basics7min
Logic-Level Timing: Basic Assumptions & Models30min
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks27min
Logic-Level Timing: A Detailed Example and the Role of Slack10min
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26min
Interconnect Timing: Electrical Models of Wire Delay16min
Interconnect Timing: The Elmore Delay Model14min
Interconnect Timing: Elmore Delay Examples14min
Reading2 leituras
Week 4 Overview10min
Week 4 Assignments10min
Quiz1 exercício prático
Problem Set #3min

Instrutores

Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

Sobre University of Illinois at Urbana-Champaign

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

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