Welcome again to FPGA design for embedded systems. In this video, you will learn how to program the target FPGA with hardware and software in the same development session. You'll learn about the limitations of the free evaluation version of the Nios II and how to resolve basic programming issues. Here's a picture of the soft processor design flow. The soft processor design flow includes two paths, on the left is the hardware development using design flow and Quartus Prime that you're already familiar with, on the right is the Nios II SBT flow. Once the hardware and the software design are complete, the last step is to program the FPGA in both the hardware configuration memory and the software program memory. The MAX 10 is unique to Altera in that it has internal flash memory for configuration, and so there are two ways to program it. One is with JTAG, as with other FPGAs using a dot sof file directly to the SRAM configuration memory cells. The other also uses JTAG but programs the configuration flash memory, which is transferred to the SRAM configuration cells on power up. JTAG programming requires a programming cable like a USB-Blaster II, or EthernetBlaster II. We'll use the dot sof method in this class. So here's how you'd go about programming the Nios II. In general, the hardware must first be programmed before loading the software, because the software download checks for the presence of a processor. This is a five-step process to program the hardware. First, connect the USB cable between your DE10-Lite kit and your computer. Second, launch the Quartus Programmer via the icon or through the Tools menu, Tools, and then Programmer. Next setup, the programming hardware for USB-Blaster. Then select the programming file and then click ''Start'' in the programmer in order to download the configuration file into your development kit. So this shows you step 2, which is to launch the programmer tool and then select the hardware setup as shown here. Then step 3, you're going to complete the hardware setup by selecting the USB-Blaster in the dialog box that appears. Then in step 4, you select the programming file by clicking "Add File". Notice here that the file is time limited. We'll explain a little more about that here in a bit. Then step 5, back into the programming window, you might have to delete any other entries that are listed. It might show another IC connected in the path within that little picture, so you need to delete that. So there's just one thing to program. Click in the upper left and you should see progress to a 100 percent in all green on the upper right. So there are some limitations to the use of the Nios II unless you have a license for it. Unless you have a license for the Nios II processor, you will obtain a message about a time-limited mega function. The message indicates exploration will occur in OpenCore Plus evaluation mode. So we are going to use this in the OpenCore Plus evaluation mode. All that means is that once the FPGA is configured, you can use the Nios II as long as you want, but when you take power off of the board, you're going to have to load it back up again. So you can't permanently store the Nios II in the device, you have to load it up every single time. It's not a bigger deal as it might sound. So as it says here, please note the OpenCore Plus evaluation mode prevents us from programming the flash to the MAX 10 device, and evaluation must occur by programming the FPGA SRAM from the Quartus Programmer each time the kit is powered up using the dot sof file. So we can't really use the dot pof file because we don't have a license for it. A window will pop up on the Quartus Programmer. Just leave this up and do not press ''Cancel'' until you are finished using the hardware design that you just downloaded because that will stop the Nios II processor. So it'll look a little bit strange. You program this device with a configuration file, and then this window will pop up telling you that there's a time limit on things. If you click "Cancel" on that, then your hardware quits working at that point. So you want to just leave that window up while you open up the IDE for Nios II, and go ahead and do all of your programming work from that point going forward. Assuming the software has been built, then to load the software into the FPGA I simply right-click on the application and the select "Run as Nios II Hardware". Other non horrible options are available but for now, assume that we want to do our debugging in the hardware with code in the FPGA. You may see a window indicating no connection was found. If so, click on the "Target Connections" tab, click on "Refresh Connections", and then hit Run. So this shows you how to solve this one particular problem that you might see. Once you refresh the connection, the software should download and begin running. You can do this from the debug perspective to get more control over the testing process. This is the debug perspective and it shows the output of the simple Hello program. In this video, you have learned how to program the target FPGA with hardware and software in the same development session, limitations of the free evaluation version of the Nios II, and how to resolve basic programming issues. Here's the references.
