Hello, and welcome back to FPGA design for embedded systems. In this course, we will talk about synchronous logic as well as combinatorial logic. Synchronous logic includes latches and flip flops. Combinatorial logic includes AND gates, OR gates, and NOR gates. If we wanted to build a latch, how would we do that in VHDL? Here's a picture of a latch with the D input, a gate control a Q output, and a clear. Here's the VHDL code for creating a D latch. In this case, we have a process sensitivity with GATE, and D as an input, we have an if, if gate equals 1, then Q gets the D output. So we have no rising edge control to create this latch, and the end of our if statement. We have no gate equals 0 value, so the latch is inferred. Here's another latch example, process number two, we have gate, d and clear as an input. If clear is 1, then q output gets 0. Else-if gate is 1, then the output of q gets d. What is combinatorial logic? Combinatorial logic is END gates, OR gates, NOR gates inverters. Combinatorial logic takes a finite amount of time, in best case or worst case to propagate through logic. In this case, the wire C, takes 0.2 nanoseconds to propagate across the wire C. The NOT gate, takes 0.9 nanoseconds, the D wire takes 0.3 nanoseconds, the END gate 1.1 nanoseconds, and the Y wire 0.2 nanoseconds. In this case, the maximum transition time through this logic path is 2.7 nanoseconds. In this case, the maximum transition time from 0-1 from the path C to Y takes 2.7 nanoseconds. This is an asynchronous path, from C to Y. If we wanted to synchronize this path, we would take our combinatorial logic, and we would add a clock and a flip-flop to the output of our Y, and now our logic has become synchronized. How would we describe in VHDL a D flip flop, D input, clock trigger, reset, and a Q output? Here's the entity, we have a D input, a clock, and a reset as input, and a q as an output. In this case, we could also use clock tick event and clock equals 1, but we've used the built-in VHDL function of rising edge of clock. So whenever we see rising edge of clock in our process, and if reset equals 1, then q gets a 0 output. Because we're inside of the if rising edge, this is asynchronous reset flip-flop, else we're still inside of the rising edge clock loop, the q output gets d. How would we create a D flip flop with an asynchronous reset? Our entity looks similar d clock set, and reset or inputs, q is an output, and here's our architecture. If reset equals 1, then our q output gets zero. This because it's the first evaluation inside of our circuit, this is an asynchronous reset, else-if rising edge clock, then if set equals 0, q gets 1, this is inside of our else-if rising edge, this has become synchronized to the rising edge of clock, if set equals 0, then q output gets 1, this is synchronous, else q output gets d, this is also synchronous. How would we make a d flip flop with a clock enable? Similar entity, d clock, enable, reset q output. Here's our architecture for a d flip flop with clock enable. A synchronous, we're looking for the reset equals 1, then q output gets 0. This is an asynchronous reset. Here's the synchronous portion of our circuit, else-if rising edge clock, then, if clock enable equals 1, then q output gets d. So this is synchronized to our rising edge of the clock. In this video, you've learned how to describe synchronous circuits in VHDL, and how to design flip flops and latches with synchronous and asynchronous sets, and resets.