In this video, you will learn how to describe synchronous circuits in Verilog, and how to design flip-flops and latches in Verilog. This is an example of the fundamental synchronous circuit, the D flip flop. Synchronous circuits are essential to the design of advanced digital circuits. The use of a clock, and an edge triggered circuit allows us to avoid logical hazards inherent and purely combinational circuits. The always block is necessary as is the posedge attribute of the clock. Q must be a reg. The flip flop is described in one line as the output gets the input on the rising clock edge. Even more fundamental than a D flip-flop is the D latch. Knowing what you know, how would you describe a D latch in Verilog? As we learned in the last video, sometimes we get latches by mistake, but how do we create one when that's what we really want? Here's the code for a D latch with and without an asynchronous clear. Note the sensitivity list includes data input as well as the clock, and that the clock is not edge triggered, so this produces a level sensitive circuit. The use of a keyword does not imply the logical or function, it's just the separator for the list. Why then don't just use commas? I can't explain. Try not to be confused by the syntax. One way to understand this is that in simulation, the always block code is evaluated when there's an event on clk, or an event on d, or an event on aclr. So the first always block gives us a synchronous type of D latch, the second always blocks gives an asynchronous D latch. So how can we describe D flip-flops then in Verilog, including those the asynchronous or synchronous reset? Here's the code for D flip flop with either a synchronous or an asynchronous clear. Note that in the synchronous case, the sensitivity list only includes the posedge clk. For the asynchronous clear, it's also dependent on the clear signal, which is active on the negative edge. If a preset is also desired, the addition of an else-if statement would create the preset function which isn't shown here. So how can we make a clock enable in Verilog? Some FPGAs include D flip-flops with a clock enable, how can we describe a D flip flop with a clock enable in Verilog? Here's the code for D flip flop with either a synchronous or asynchronous clear and a clock enable. Note that the sensitivity list does not require the clock enable signal, as any change in output is dependent only on the clock or the asynchronous clear. In this video, you have learned how to describe synchronous circuits in Verilog, and how to describe flip-flops and latches in Verilog.