Hello, and welcome to FPGA design for embedded systems. In this video, we will learn about finite state machines and the rationale behind using finite state machines, how to create a finite state machine, and criteria for determining which state of encoding format to use. Finite state machines are very important part of digital design and software design too. The state machine concept provides a highly reliable, maintainable, and methodical way to design circuits that perform a sequence of operations with great predictability. State machines are always in a known state. Good designs make use of finite state machines. Finite state machines are categorized into two types; moore or mealy. Moore state machines only depend on the output of the state. Mealy state machines depend on the output of the state and the inputs. In this flow diagram, you can see that the inputs flow to the output logic as well as the current state to give us a mealy output, and for the moore outputs on the far right, it's only dependent upon the current state, and our state transition is based on a clock and a reset. Here, we have a state diagram showing the angles as we proceed through a process for machine control. Angle 0, angle 45, angle 90, 135, 180, 225, 270, 315, and back to zero. We have some controls move counterclockwise, move clockwise, or don't move at all. If we're in angle 0, we can move forward to angle 45 degrees. If move clockwise is set, we could move backwards to angle 315. If move counterclockwise is set or we can stay on angle 0. Here, we have a state table showing our current state, and our next state, and our desired outputs at each state. Here, we have a chart with state encoding types; binary, Gray, Johnson, and one-hot. In a case of binary encoding, it's just like any other binary counter. 000, 001, 010, 011. In the case of gray code, Johnson code, and one-hot, we only have a single transition between bits as we transition through states. In the case of binary, where we go from transition 1 to transition 2, we have bit 0 changing from 1-0, and we have bit 1 changing from 0-1. So we have two bits changing as we go from state 1 to state 2 with a binary counter. In gray code, Johnson code, and one-hot code, we only have a single bit at a time transitioning. In the case of going from state 1 to state 2 of our gray code, we go from 001 to 011, only a single bit is transitioning. In the case of Johnson code, same story, 0001 to 0011 only a single bit is transitioning, and in Johnson code we have a one's flow through and then zeros flow through shifting to the left. In a one-hot state machine, we only have a single bit, a single flop set to one at each state. In VHDL we can create a table for our numerated design. Angle 0, angle 45 using a binary counter. Here, we have our port declaration, clock reset, move clockwise, move counterclockwise, our physical position of state width minus 1 down to 0. Our desired position and our position error of state width minus 1 down to 0. These are our outputs. In the beginning of our architecture, we can create local signal called current state and next state, also a standard logic vector type state width minus 1 down to 0, and begin our architecture. Here, we have two processes; a combinational process and a clock process to take us through the state. In our combinational process, we're looking at our sensitivity list based on move clockwise, move counterclockwise, our physical position, and current state, and we're going to create a case statement. Whenever the case of the current state is when angle 0, if move clockwise equals 1, then our next state gets angle 45 else-if move counterclockwise. We're going to go backwards one state to angle 315, else, no change, so we're going to stay on our state of angle 0. When we're at angle 45, we move forward one angle to 90, If move clockwise, if move counterclockwise is set to one will move backwards to angle zero. Otherwise, stay on this state. We'll describe all of our states, angle 90 through angle 315, and here's our last angle 315. If we have moved clockwise forward, then we'll move to angle 0. If we have moved counterclockwise one then we'll move backwards to 270, else, we'll stay at the state. Again, whenever we create a case statement to find out when others and in that case, we're going to set our self to angle 0. Here we have our clock process which will step us through our states. So anytime clock or reset changes in our sensitivity list, we will evaluate, and here's our asynchronous reset. Upon asynchronous reset, if reset equals 1, our current state equals the physical position. Else if we see a rising edge of clock, then our current state gets Next state and End a process. Outside of the process, we can set our moore output. Remember moore is only based on the current state. So our desired position for our moore output is the current state. Our mealy output of position error would be based on the current state and an input which is the physical position, so our position error would be set to desired position minus physical position, and end architecture. This is the RTL view from Intel Quartus prime after implementation in a MAX 10 FPGA. Notice only three flip-flops are used for the current state register at a total of 17 logic cells are used. This is a very efficient sequence or design. Looking at the code, one may not have expected such a result with a very small number of circuits. After running an experiment inside of the tools, we find that when we encode binary, gray code, Johnson, and one-hot, we get a difference in total logic cells consumed, 17 for binary, 29 for gray code, 51 for Johnson, and 146 for one-hot. Now in this case, we may be looking for efficiency, we may be looking for speed, or we may be looking for total area. That's an Engineering call. In this video, you've learned the rationale for the use of finite state machines, how to create finite state machines, and some criteria for determining what state of encoding formats to use.