Here is the diagram of a basic control system, feedback loop. that we or that I introduced at the beginning of this week. so the goal now or for this week has been to model the elements around this feedback loop that we can use in our upcoming week to design the control system. So, what we've done so far this week is derive an AC equivalent circuit for the switching converter that models its dynamics. So now we have that. Let's look at the rest of the loop. The feedback connection, summing node and compensator are generally built with analog circuits such as off amp circuits. And I'm going to presume that you already know how to solve those and design them from other classes. But the thing that's missing is the pulse width modulator. And so we need to take a few minutes now and discuss how the pulse width modulator works, and how to model it. So the pulse width modulator is a circuit rhat has an analog control signal at its input, we're calling VC, is some smooth signal. And it's output is the gate drive signal that switches high and low. when it's high the mosfet is on, when it's low the mosfet is off. And the duty cycle of this waveform is supposed to be proportional to the control signal VC. So let's talk about what is that relationship between the duty cycle and the analog input VC. Here is a common way to build a pulse width modulator. We have a saw-tooth wave generator which is an oscillator, and it produces a signal such as this one. This is also sometimes called a ramp generator. so, it makes a periodic signal, whose period is the switching frequency here. So this is the switching period, t sub s. And, in fact, this saw-tooth wave generator is what sets the switching frequency of the switching converter. Here I've drawn the, the saw-tooth waveform, V saw T as being this function that starts at zero and it increases linearly with a constant slope up to some maximum value v sub m. at the to slip into the switching period, then it jumps back down to zero and starts over again. The saw-tooth wave is put into an analog comparitor circuit where it is compared with this control input, the analog input VC of T. VC of T is this wave form right here. The function of the analog compartor is that it compares the two analog input signals at it's plus and minus input terminals, and it produces an output logic signal that is high when the plus input is greater than the minus input. And otherwise, it's low. So, this pwm output then will be high, here until at this point the saw-tooth and the control input are equal. After that point, the saw-tooth will be greater than VC and the logic output will switch low for the rest of the switching period. So the output of the comparator is then this logic signal having a duty cycle of d. What is the equation between the input and output of the pulse-width modulator? Well if the saw-tooth waveform is linear, so it has constant slope, then we can write that the duty cycle is actually linearly proportional to, to the control input VC. And you can compare or look at just a few different cases suppose VC is zero then we'll switch at the very beginning and our duty cycle will be zero and on the other hand if VC is equal to the peak value of VM, then we won't switch until the end of the period and our duty cycle will be one. And with a straight line, or linear sawtooth, the duty cycle will vary linearly in between those two extremes. So we can write then, that the duty cycle is the control input divided by the, the peak amplitude of the ramp. V sub M. Sometimes commercial saw-tooth or pulse with modulators have saw-tooth waves that start at some dc bias, or some value greater than zero. And in that case, we need to subtract that bias from VC in this formula. So here is that equation again. If you like, we can perturb and linearize this equation. So we let VC equal capital VC plus VC hat, but d equal capital D plus d hat. If you plug those into here, we get this expression. And from these we can see that the quesen or steady state value capital D is equal to capital VC over VM this is in fact a practice how the quiescent duty cycle is set by the DC component of the control voltage we've seen. And likewise D hat is equal to VC hat over VM so the block diagram of the pulse with modulator then is a gain. Equal to one over VM. and in a small signal sense then, DC hat goes in and D hat comes out. I should note one other thing; the pulse width modulator effectively samples, it inherently samples. which means that we have one duty cycle per switching period. If we go back and look at these wave forms, the duty cycle is determined only at this, at this point right here, and there is simply one value of duty cycle here over a switching period that is proportional to the, the voltage, VC, sampled at that instant. It doesn't matter what VC does at other times. So we can have things going on here at, at other times and they won't effect the duty cycle. Now you might say, well suppose we actually had variations that did this, and made it switch many times. That's actually an undesirable thing. It causes a lot of switching loss. It can happen when there is noise in our control signal, but we do everything we can to eliminate it. One thing that's often done in commercial pulse width modulator chips is that there's a latch driven by this comparator. The latch gets set by the saw-tooth wave generator, at the beginning of the switching period, and it gets reset by this comparator signal and then the output of the latch is this signal that goes to the gate driver. What this does, is it sets the latch here to turn the fet on, or mosfet on, or whatever our switch is. At this point, the transistor's turned off, and once it's off, no amount of noise can turn it back on again. Okay. So we have sampling then, there is one value of duty cycle for every switching period. Regardless of, of VC, and we have a sampler built in. sampling is actually beyond the scope of what we're going to talk about in this course, but what I'll say is that we must restrict our, the bandwidth of our control system. To be sufficiently less than the nyquist trait which is half the switching frequency or half the sampling rate. models of the modulator that don't account for sampling therefore are not going to be accurate except at frequencies that are sufficiently less then this nyquist rate. One quick summary slide something sampling does is it repeats the spectrum of the signal at the switching frequency in its multiples and so we get something that is known as alias, aliasing where the original signal hs frequency content at dc and low frequencies that frequency content gets folded by aliasing up to higher frequencies at about the switching frequency. And its harmonics. Though we're not predicting that in our models, and in fact when there is aliasing generally bad things happen to our control system and so we don't want that to happen. Here is a plot of the effective transfer function of the zero order hold circuit which is what the host width modulator behaves as that I've described so far. and so, it has behavior at the Nyquist rate and higher and generally what we want to do is restrict our bandwidth to be sufficiently less than that. And at these lower frequencies the modulator essentially has a constant gain that is the one we already discussed, the one over V sub M. So for frequencies sufficiently less than the Nyquist rate, we can model the pulse-width modulator with a simple gain block. With a gain of one divided by the peak to peak amplitude of, of the saw-tooth. And this is the model that we're going to use then in our control system designs that are coming up in the future weeks.